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FPGA implementation algorithm

$10-30 USD

En curso
Publicado hace más de 7 años

$10-30 USD

Pagado a la entrega
I have an algorithm and i need to write vhdl code read any image then apply this algorithm and get me the out put
ID del proyecto: 11746125

Información sobre el proyecto

16 propuestas
Proyecto remoto
Activo hace 7 años

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I think i can help you a lot
$30 USD en 5 días
3,4 (1 comentario)
0,2
0,2
16 freelancers están ofertando un promedio de $27 USD por este trabajo
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A proposal has not yet been provided
$20 USD en 1 día
4,9 (483 comentarios)
8,2
8,2
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Hello! Please check my reviews to know a bit about me! Thank you
$25 USD en 2 días
4,9 (81 comentarios)
6,2
6,2
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Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency
$25 USD en 1 día
4,9 (5 comentarios)
4,5
4,5
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A proposal has not yet been provided
$25 USD en 10 días
0,0 (0 comentarios)
0,0
0,0
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Ph.D ECE major at Georgia Tech. Good at C Programming and RTL Design using Verilog. 2 years experience in industry
$35 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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A proposal has not yet been provided
$15 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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previously worked on Image processing based project on FPGA boards.
$30 USD en 4 días
0,0 (0 comentarios)
0,0
0,0
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I have 12 years experience in VHDL development. I have implemented various algorithms for FPGAs for signal processing and communication protocols.
$25 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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Hello, I can do this project. I am expert in FPGA, VHDL, Verilog. I have done no of project on this technology. Please open your chat box for more discussion. I have 4 year experience in this field. I can do your project easily.
$25 USD en 1 día
0,0 (0 comentarios)
0,0
0,0
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Hello, We are a team of embedded hardware and software professionals with experience in VHDL code and FPGA implementation. Would like to know more details about the project. Looking forward to work on this project. Please feel free to contact us for any further discussions. Thanks and Regards EmWorld
$45 USD en 7 días
0,0 (0 comentarios)
0,0
0,0

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Bandera de JORDAN
Jordan
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Miembro desde oct 28, 2015

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