FPGA designer using VHDL and/or Verilog for Xilinx and/or Altera FPGA(s)

Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No other work is needed at this point. I will provide a Xilinx Spartan III demo board made by Digilent ([login to view URL]), if necessary and have it shipped to the developer. The developer is welcome to keep the board.