Open CL algorithm based FPGA Miner

Greetings, I am an RTL Design Engineer, specializing in ASIC and FPGA design. I have used tools like sdAccel by Xilinx and have done projects with openCL to netlist as well. I will spend a day or two to understand the project and analyze the algorithm, coming up with possible test cases and failure states. after this I will design the hardware implementation at a micro-architecture level which should take about a day at most. Another day I will spend in writing the RTL and doing Lint checks. Days 5 and 6 will be used for writing a test bench, verifying the RTL and generating test reports. If you require FPGA synthesis, I can do that too on a Intel Cyclone V or Arria V board. Hope you find this proposal meaningful and worthwhile. Thanks and regards, Jim Your friendly neighborhood RTL guy

I tried to convert AES algorithm into FPGA platforms. Also I am very familiar with FPGA. I am now working as an FPGA prototyping engineer in an ASIC company. I am very interested in the project you posted. If it is possible, I would like to know more about what do you want to do.

I'm an experienced hardware developer in the Silicon Valley bay area, CA working on security algorithms implementation in ASICs. I have extensive experience writing HDL code and making sure it is synthesize can meets timing closure. Previously, worked with FPGAs chips from Altera, Xilinx and Microsemi and thus have wide experience using vendor tools, debugging and also delivering successful hardware. Simultaneously, experience in writing diagnostic code using Ansi C/C++ and Open CL procedures and function calls. Therefore, i am suited as a candidate for this project and will be a good communicator and guarantee to deliver accurately on time.

Now, I am develop the Bitcoin miner on FPGA. I create specification., write RTL and run VCS, I will implement on FPGA