Simple VHDL audio project - repost

Since HDL designs describe digital hardware systems for implementation on FPGA’s and ASIC’s, HDL is an ideal tool to design realtime digital signal processing algorithms. This project involves the design and implementation of such digital signal processing algorithms in the field of audio/sound effects.

The goal of the project is to perform some realtime audio processing on a streaming audio source. The result of the processing should be streamed to

some speakers. The development board (Digilent Atlys) contains an audio codec chip (Realtek), a line-in, a microphone and a line-out interface. The chip forms the interface between the FPGA and the audio source/speakers. This implies that some logic has to be made to have access to and to control this audio chip. The FPGA should get its audio from the line-in and/or the microphone input (for example you could use your laptop on the line-in (music) or a microphone on the mic-in (speech), but initially start with one audio input though). The same chip is used to stream the processed audio to the line-out interface.

Some sound effect/altering algorithms should be implemented in the FPGA to do the processing on the streaming audio. Initially start with some basic filter (FIR, lowpass, highpass, notch). These would be on/off controlled by the switchers on the board.


Digilent Atlys FPGA board

Xilinx development software

PC speakers

Audio source (mic, laptop, ...)

Habilidades: Electrónica, Ingeniería, Microcontrolador, Arquitectura de software, Verilog / VHDL

Ver más: audio vhdl, software development algorithms, simple design tool, simple algorithms in c, line algorithms, implementation of algorithms, hdl hardware, fir filter design, digital design audio, development of basic algorithms, development of algorithms, architecture design on line, algorithms implementation, Algorithms development, pc board design, audio engineering software, architecture designs, xilinx, vhdl, vhdl fpga

Información del empleador:
( 5 comentarios ) Prague, Czech Republic

Nº del proyecto: #5170271

5 freelancers están ofertando el promedio de $313 para este trabajo


Hello! I can deliver you a functioning solution in 1 month (20-25 working days). I have access to the Atlys board, I also own logic analyser. I will also provide a documentation suited to your needs (~50pages). R Más

$1111 USD en 3 días
(5 comentarios)

I am Electronics and Communication Engineering Graduate From Ain Shams University In Egypt I took several Courses in VHDL beside our study courses in College I am familiar with modelsim and XLinix and I read the Más

$55 USD en 6 días
(0 comentarios)

hello We can able to do this task very effective manner also deliver it on time... Tech support will be provided to you. if any clarifications we will assist you from our end... waiting.

$78 USD en 4 días
(0 comentarios)

I Have seen [login to view URL] can do the project for you. we have the team of [login to view URL] provide you the quality work. The question is why you choose us? We have 5 years of experience in the android market have done several Más

$100 USD en 3 días
(0 comentarios)

Dear Sir I am a telecommunication engineer, I already have very good experience with digital Filter design using VHDL (reference of a project done in Polytechnique Montreal, CANADA : [login to view URL] Más

$222 USD en 7 días
(0 comentarios)

Hello and thank you for considering my candidacy. I would like to help you achieve your goal for this project. My skill-set appears to align well with your requirements. One minor item of note is that the schematic Más

$333 USD en 5 días
(0 comentarios)