verilog assignment

Dear sir I have more than 10 years experience in digital design using verilog, please check my profile also please message me so that we can discuss Best regards

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hi, I am a highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Kindly contact me for further discussions. Thanks, Loi

Hi, I'm an electronic engineer with more than 5 years of experience in Verilog programming and FPGA based systems development. I've decided to apply for the project as I have many experience in developing RISC processors development. I can see you have some work done so far and I'm confident on completing the project for you successfully. Given my experience I can assure that. Looking forward to hear from you. Thank you Anusha

Hi, I am mechatronics engineer , professional at verilog . I can do all you need , So,contact me for further details

I have already done some RISC projects before. I will finish your project on time. Please award it for me.

Hello, I am working in the ASIC design flow for 10 years. I have experience in using VCS FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for design multi core chip with 16 core of 16bit MIPS such that I think I can do your task very well. Please see reviews in Verilog project which I complete very well, please ignore a bad review in a website project review. Best Regard.

I am professional FPGA programmer with over 10 years of experience in processor logic design and development.