BASYS Verilog code implementation

A proposal has not yet been provided

A proposal has not yet been provided

I would like to bid this job because I am really suitable for job description: First: I am an C++/C/Mathlab/Electronics engineer who is very familiar with C++/C/Mathlab/VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Especialy, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report.. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

i had done ms in digital system design. also i had 8+ years of experience in the field of fpga, verilog hdl. i can do this task for you

Hi i have basys 2 board with me , so I can easily implement and test the code . please let me know how to take this further for fruitful accomplishment of this project thanks sk

i have over 8 years of experience working with Xilinx FPGA and have a completion rate of 100 percent. Can you please specify what should of improvement and optimization are you looking for. i mean are ytou looking to improve 1. Timing 2. Area 3. Dynamic power or anything else

Selam, projenizi uygun fiyata 2 günde yapabilirim. projeden haberim de var zaten başka bir arkadaş da ulaşmıştı bana

A proposal has not yet been provided

Hi, I am sorry if the simulation is not as good as you expected. I tried to finish without any error, to explain everthing by commenting in code. And I thought that you can understand all of them. I hope that you would give me an opportunity to finish the 2nd part of this project. Thanks Luffy08

I can complete the work just let me know what needs to be done . I will require the payment before delivery

I am an working ASIC, FPGA designer, If you are interested I can make this project for you. see my linkedIn profile for more information.