Assembly language program
$10-30 USD
Pagado a la entrega
Details: The purpose of this project is to help solidify your understanding of the details of how caches and memory work by building a multi-level cache and memory model that processes address traces concurrently on a dual-core CPU. Your caches must support several design options and be configurable. For example, your cache simulator should support different sizes (number of entries), different cache line sizes, and different levels of associativity as described in the following sections. You will need to maintain hit/miss ratio statistics as well as a running average of instruction latencies during execution that will be aggregated into reportable performance metrics upon completion of address trace processing.
I will send detail if you are able to do it.
Budget 75$
Deadline March 17
Nº del proyecto: #7260747
Sobre el proyecto
2 freelancers están ofertando un promedio de $112 por este trabajo
Hello, I have used a few cache simulation tools, but I have never made my own simulator. I might be able to do this project. Please provide more details.
Hi I am Dinh. Hope to work with you. >>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>>>>>>>>>
