Design & Implementation of Digital Finite Impulse Response (FIR) Filter on Cyclone II FPGA

1. Develop the FIR digital filter structure on FPGA Cyclone II available on Altera DE1 development platform. 2. Evaluate the performance of the FIR for different filter taps. 3. Identify the criteria to enhance performance as compared to its 1st order and 2nd order analogue filter counterpart. 4. Acceptable bandwidth specification for audio application with good justification. 5. Conduct real-time simulation experiment such that the input test signal is generated synthetically on FPGA, side by side with the filter. Using fdatool in MATLAB to generate the filter coefficients. Using Quartus II (Altera) software is a must for FPGA. The filter tap orders do not need to be so high. 8, 16 and 32 taps is sufficient.