A single precision floating-point adder (FP ADD)

Dear sir I have more than 7 years experience in digital design using fpga I know exactly how To design floating point adder and perform all required simulations and analysis using xilinx ise

Hello , We have a team of Skilled Java-J2EE professionals with experience up to 8 yrs. You will be able to directly communicate with our technical expert. Our Expertise is J2EE: 1) Frameworks: Struts, Spring , Hibernate , Lucerne, Quartz, Ant, , Cruise Control, jUnit, DbUnit, Mybatis 2) Web Technology: JSP, JSTL, JSF, JQuery, Ajax, Java Script, DWR, FCK Editor, Extjs 3) Application Servers: JBoss, Web logic, Web Sphere, Apache Tomcat, Sun ONE 4) Payment Gateway: PayPal Integration, can integrate any other payment gateways too 5) Tools: Maven, Ant, xDoclet, iReport 3.6 Jasper Report (with iReport), ceWolf API (charts), Maxmind GEOIP API, Atlas Device, Flow Player integration, Google Analytics, adMob Analytics, Google Adword, YouTube API, Document Viewer Integration, Display Tag Libraries, Fusion Charts API, ammap API. More details will be provided on request. By doing this work, we are interested in developing long term relationship by displaying our quality. Thanks for reading our proposal. Regards.

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I can help you right away! Please accept my bid to begin working at your project! I can finish your project in 4 hours maximum! Hello! If you have digital design projects I can help you right away! I have 8 years experience in designing digital logic circuits using VHDL and implementing them in Altera FPGAs. I was a digital design engineer at Grenoble Institute of Technology! Right now I am a teaching assistant at an important university in Europe. I teach the digital logic design and VHDL modules laboratories! Have a nice day!

I am having 10+ Years of experience in the same area but one thing I can do this job for you , I have xilinx ISE 14.2 with me . please let me know when and how can we discuss this further ? I am available on skype and Gtalk for further discussion . I have quoted the amount for following tasks 1) Floating Point Adder Verilog Code 2) Random Automatic Testbench 3) Synthesis , P & R Report 4) Optimizations and Speed Calculations Waiting for your response. Thanks Shobhit Kapoor

Dear mariam, I am interested in undertaking your project. I have large experience with both VHDL and Verilog HDL as a seasoned expert for more than 15 years. The design will be implemented in Verilog HDL adhering to the RTL coding style. For previous designs of mine you can Google for kvcordic or hwlu or check my previous work on Freelancer. Thanks!

Hi mariam91 I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 8 years experience in digital design and well acquainted with ISE, NCverilog, EDK embedded tools. I have completed 10G data traffic project where software part is implemented using Microblaze to configure NELOGIC chip via MDIO protocol & send real time results of 200 registers to PC via uart protocol. The custom IP written in mixed Vhdl / verilog used to handle 10G data Traffic. Recently for client I have worked on floating point pipelined MIPS processor where Floating Point Add Single (add.s), Floating Point Subtract Single (sub.s), Floating Point multiplication Single (mul.s) , Load Floating Point Single (lwc1), Store Floating Point Single (swc1), Floating Point Compare Equal Single (c.eq.s) and Branch on Floating Point True (bclt) instructions were performed. Following single precision floating-point stages were added. 1. Calculation of exponents & shifting accordingly. 2. Addition of the fractions 3. Normalization & Rounding 4. Normalization & Check of overflow. All the logic implemented in verilog. I have read your project requirement and can achieve the results you are seeking. I am free and can work upto 40hr/week. Further we can discuss it and I look forward to receiving your response. Regard Mahar

Have been working in C and VHDL for a very long time . Can provide better 24 Hour customer support. I have a team that can finish your work very soon.

I had masters in VLSI and lot of experience in verilog/vhdl. I had worked on single and double precision floating point multipliers as my thesis work. so i can complete your project with in one day .Check my profile if you want to know about my rating and reviews . Pay me after you completely satisfied with the work. :-) regards. kiran

Hi, I am an Electrical Engineer recently graduated and currently working in the Embedded Industry. I am skilled with hardware design in Verilog HDL. I designed a simple RISC processor in my Digital Design course using Xilinx during my Engineering studies. I learned floating point adders during Computer Architecture course. Designing a floating point adder in Verlog would be a joy for me. Please reply if you find me eligible for this project. Best Regards

I can deliver the code for you in 5 working days. I will respond to all requirements stated in the project description. Regards, Botond

FP addition is a tricky and each part(sign , exponent and fraction)needs to be handled precisely it involves the following steps: => de-normalization => addition => normalization Having functions for each of the above step in verilog will be the approach for implementation The desired functionality can be completed in a week but have mentioned 10 days just to keep a marginal time. Awaiting your response...

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Hi, I will be able to implement it in VHDL on a Nexys 3 FPGA borad (Spartan 6), with which I already have experience and I will be glad to get more details about the project. Regards, Alon

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset Characterization of FPGA”. In addition I had a one year experience to work with Physical Research Laboratory (PRL), Ahmadabad. In PRL I was working on Chandrayan-2 payload design where I had developed a DAQ for X- Ray florescence for elemental analysis

I wrote code IEEE 754 32 bit FP_adder system verilog design code and verilog testbench code. I have stimulus with only two positive floating number. I have simulated it with modelsim. If you want it, I can give it. ( I tested it completely) Thanks.