DDR2 Controller - open to bidding
$250-750 USD
Pagado a la entrega
Design a DDR2 memory controller as per the attached PDF. The target FPGA is XC6SLX45-3CSG324C, and the DDR2 memory is MT47h64M16HR-25E. The DDR2 is configured with 4-x 32 bit ports. All the brown blocks on the schematic are Xilinx Coregen parts (DDR2 controller and FIFO memory).
4 VHDL components need to be written (green boxes).
1- FIFO-IN_CNTL
This component will constantly read the FIFO and write the data in a circular buffer in the DDR2 memory. The circular buffer will be defined from address 0 to the 32-bit (DDR2-size) signal parameter.
2- FIFO-OUT_CNT
This component will constantly monitor the FIFO Full pin, when it is no longer full, you will read the DDR2 memory and fill the FIFO (always keeping the FIFO full). The DDR2 will be a circular buffer defined from 0 - the size parameter
3- The thrid component is the wishbone controller. This is a slow speed interface, and the component will be used twice (ports 3 + 4). The Wishobone interface should support 32bit, 16bit and 8bit reads/writes
4- The forth component is a simple timing block which takes the 50MHz input clock and generates what ever clocks are needed for the design.
Finally, the [login to view URL] file is required to link all coregen and vhdl components together, along with a constraints file.
Nº del proyecto: #5400988
Sobre el proyecto
14 freelancers están ofertando un promedio de $1280 por este trabajo
Dear Hiring Manager, I can do this project for you. As I am working on the other projects also, so the minimum time I require is 40-50 days for this and the price can't be reduced by bargaining (however after discus Más
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Specification related questions: - You mention a block diagram, but there I din't find it. But I think from your description almost every element is clear. (A block diagram would be great) - Probably there are 2 inte Más
Hi, We have 14+ years of exp in FPGA design for Xilinx, Altera and Actel devices. We didn't see any attachment in your posting. Please share the details to provide you the cost and time estimation. Looking forwar Más
