Cosa and csa based 32 bit unsigned multiplier

Adjudicado Publicado Aug 13, 2014 Pagado a la entrega
Adjudicado Pagado a la entrega

In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it’s performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).

Electrónica Verilog / VHDL

Nº del proyecto: #6316791

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3 propuestas Proyecto remoto Activo Aug 14, 2014

3 freelancers están ofertando un promedio de ₹27387 por este trabajo

botzindia

Hi, We are a team of electronics&embedded engineer with more than 10 years of experience in designing and developing various digital and embedded systems... We have done a lot of projects in VHDL. Also we conduc Más

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TechnocracyPune

I am experienced in verilog and VHDL. In fact I have developed such multiplier in past as well. Hope you will enjoy working with me. -Jigar

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