Designing of Ripple carry adder and carry look ahead adder using low power techniques MTCMOS ( Multi threshold CMOS technique), Power Gating, Dual Stack, GALEOR and LECTOR

we are using the proposed techniques to reduce leakage power such as MTCMOS ( Multi threshold CMOS technique), Power Gating, Dual Stack, GALEOR and LECTOR. RCA and CLA circuita designed by using the above mentioned techniques, power dissipation is calculated for each technique and is compared with general CMOS logic of RCA and CLA. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent. We need simulations. Tools used for simulation must be Modelsim, Hspice, LT spice, Xilinx