Verilog vhdltrabajos

As part of this project, I need assistance in performing the following tasks: - Writing VHDL code - Designing FPGA circuits, specifically for Xilinx FPGA The goal is to achieve PWM via VHDL and PS to PL UART communication in the FPGA circuit design. It would be advantageous if you have a strong background in VHDL, FPGA circuit design and specific experience with Xilinx FPGA. Additionally, understanding of PWM and UART communication would be beneficial. Estoy buscando un ingeniero FPGAs y firmware para q haga un pequeño proyecto para hacerlo correr en una tarjeta de desarrollo Pynq-Z2 con el Sw Vivado. Se trata de implementar un PWM de valor de entrada variable, esto en VHDL para cargarlo en la PL de la Zynq. Se trataría de lo siguiente; a tr...

Soy un estudiante de ingeniería electrónica que necesita aprender VHDL, XILINX y dsp. Busco alguien que pueda crear un conjunto de tutoriales en vídeo, audio y texto para ayudarme a debugear y escribir código. Estoy buscando tutoriales y clases para diseccionar y detallar algunas aspectos de un proyecto Estoy ansioso por encontrar alguien para ayudarme a que logre mis metas de aprender estás herramientas y que me sienta a gusto cuando they llegue la hora de aplicarlo.

Proyecto en xilinx empleando VHDL, clases y verificación de códigos

Implementar, simular FFT en entorno xilinx o alguna plataforma similar , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota, ante cualquier duda estoy abierto a conversar

A partir del codigo de cisfrado, que facilito. Implementar el codigo para descifrado. Para ello se Implementará el algoritmo de descifrado y comprobarás su funcionamiento usando el mensaje cifrado como entrada y la clave operativa (MSBF). Si la simulación es correcta, el resultado será un bloque de 64 bits a cero (u ocho bytes a cero). A continuación, descrifrarás el mensaje cifrado que faciltaré con la clave operativa asociada. Y colocarás el mensaje en claro en la caja de texto de la tarea. Se proporcionará todos los archivos, claves en privado. Se necesita para el día 2 de Noviembre, es una tarea de estudios, fácil. El tiempo estimado de trabajo es 30 min porque el codigo de cisfrado lo tengo, solo es modif...

Diseño de circuito VHDL en vivado

Buenas! Veréis tengo que hacer el TFG, tengo casi hecho el código en VHDL, pero yo creo XILINX me vacila. Tengo que entregarlo antes de diciembre y necesito que alguien me lo consiga a hacer porque yo solo no lo saco. Adjunto las entidades que tengo hechas, esta casi todo ya escrito solo me falta que me funcione, que no se por que, pero no me funciona.

Requiero un contador / cronometro que pueda contar de 0 a 99.9 segs, se debera entregar codigo fuente en VHDL / Vivado asi como resultado de simulaciones

Hola Miguel Angel, dominas VHDL? Si es así creo este proyecto para hablar contigo más ya que tengo un requerimiento pequeñito para resolver. Seguimos hablando por aquí.

Hola Jorge Eduardo, como estamos? Dominas VHDL? Necesito un poco de ayuda con un pequeño proyecto. Seguimos hablando por aquí.

Hi Jorge Luis, necesito ayuda con una cuestión de VHDL bastante sencilla si fuera posible. hablame por aquí y concretamos. es un poco urgente

Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo que lo implemente en código VHDL.

Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas.

El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware disponibles en el módulo de test. El proyecto abarca por tanto los aspectos de verificación funcional, descripción de hardware empleando SystemVerilog, implementación de un sistema digital integrado ...

El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware disponibles en el módulo de test. El proyecto abarca por tanto los aspectos de verificación funcional, descripción de hardware empleando SystemVerilog, implementación de un sistema digital integrado ...

Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock, prender los (o algún) led. Se deberá implementar algún tipo de barrido multiplexado para el uso de los 4 dígitos “7 segmentos”.

necesito transmitir datos numericos entre la fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en form...fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un p...

Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.

Modificaciones y rutinas extras para- gestión de dispositivos procesado de imágenes video / foto reducción de tiempo de procesado Ubicación Tres Cantos, Madrid Conocimientos de FPGAs / VHDL un plus trabajo a realizar en Abril 2017

Controlar la velocidad de un motor mediante PID usando encoder, en lenguaje VHDL para la tarjeta Basys 2 Spartan 3.

Ascensor 4 pisos, mediante una targeta basys 2 en una spartan 3e

necesito realizar proyectos en la tarjeta Nexys 2 vhdl del fabricante que tiene el procesador spartan 3E de xilinx practicamente lo que busco es un manual tecnico de como descargar los softwares necesarios para el trabajo, describir paso a paso de como realizar un programa utilizando el puerto vga de la tarjeta , en concreto un programa completo basado VHDL que me permita con este programa piloto modificarlo para generar otros programas  basados en el puerto VGA  

Realiza un circuito básico de PWM donde el tiempo en alto pueda modificarse en pasos de 10%. Simula el circuito y comprueba su funcionamiento. Deben verse varias consignas, compronado que la anchura de la salida es la correcta. Para este apartado puedes realizar una compilación funcional. ? Cambiando el tipo de compilación a no-funcional, compila el diseño eligiendo el dispositivo FLEX10KRC240-2. Utiliza las herramientas de MaxPlusII para obtener la frecuencia máxima de trabajo a la que puede funcionar el sistema. Mirando la información que aparece en el report file (fichero .rpt), indica el porcentaje de recursos lógicos que ocupa tu diseño. ? Escribe los resultados en un documento y mándaselo al profesor, junto con un archivo...

Particular busca urgente programador para tarea REMUNERADA en vhdl (facililla). Se trata de una práctica de 3º de telecomunicaciones para entregar en 10 días. Texto tarea: Realiza un circuito básico de PWM donde el tiempo en alto pueda modificarse en pasos de 10%. Simula el circuito y comprueba su funcionamiento. Deben verse varias consignas, compronado que la anchura de la salida es la correcta. Para este apartado puedes realizar una compilación funcional. ● Cambiando el tipo de compilación a no-funcional, compila el diseño eligiendo el dispositivo FLEX10KRC240-2. Utiliza las herramientas de MaxPlusII para obtener la frecuencia máxima de trabajo a la que puede funcionar el sistema. Mirando la información que apar...

Soy de colombia Programar un juego llamado simon dice En VHDL y en el programa llamado Xilinx Simón dice Colores  El juego Simón dice colores es un juego de memoria donde el jugador deberá seguir la secuencia de colores que “Simón”  aleatoriamente va generando.  cada uno asociado con un color (verde, amarillo, azul y  rojo). Cada acierto de la secuencia completa de colores por parte del jugador incrementa el nivel y Simón agrega un nuevo  color a la secuencia. El juego termina cuando el jugador se equivoque o cuando alcance el número máximo de niveles para  los que fue diseñado el juego, el cual en ningún caso deberá ser menor a 32 niveles. 

...custom boards that combine an FPGA-based signal generator with several ESP32 modules. The immediate gap is in analog and digital circuit design: I need a fresh set of eyes to review, debug, and improve the front-end and conditioning stages so our multi-channel waveforms stay clean from kHz up into the low-MHz range. You will also find yourself touching the programmable logic; I use both VHDL and Verilog, so fluency in either (or ideally both) is welcome when tweaks to the signal-generation core are required. On the microcontroller side each ESP32 handles data processing, manages communication protocols, and drives attached peripherals, all written in C/C++. Expect to dive into that firmware whenever hardware changes ripple upward. Key objectives • Analyse and ...

...bus activity. Solid knowledge of USB/PCIe link training, BAR mapping, and DMA engines is essential. The host application should be written in modern C++ or C#; it will initiate read/write calls, parse common game data structures, and integrate stealth measures against EAC, BattlEye, and Vanguard without interfering with legitimate system processes. Deliverables • FPGA bitstream + source (Verilog/VHDL) • Windows 10/11 host executable with full C++/C# source • Well-commented code and build scripts • Developer documentation that walks through setup, firmware flashing, API usage, and anti-cheat mitigation tactics • A short demo that captures player coordinates and health from a current FPS title to prove reliability and throughput Acceptanc...

...my bench, and guide me from concept through verified implementation. The immediate need is flexible: you might end up drafting fresh schematics for a small FPGA-based subsystem, debugging timing faults in an existing logic chain, or simply showing me how to streamline test-bench simulations so I can spot issues earlier in the cycle. Your familiarity with tools such as MATLAB, LabVIEW, or VHDL/Verilog will be invaluable—feel free to lean on whichever environment you know best as long as it gets us to reliable, reproducible results. I’ll share all current documentation, measurement data, and constraints as soon as we connect so you can propose a clear plan of attack. Deliverables will include: • Verified logic design or fix, shared as source files and a...

For my current project I need a custom logic circuit created and fully verified inside Intel Quartus Prime. Once the job begins I’ll forward the truth table and timing requirements; from there, the work involves writing the VHDL or Verilog, setting up the Quartus project and pin constraints, compiling to a clean build, and running a simulation to prove the behaviour. Deliverables • Complete Quartus Prime project folder (.qpf, .qsf, source, constraints) • Generated bitstream (.sof) and simulation waveforms • Brief README outlining build steps, clocking and any device-specific notes Acceptance criteria – Project opens and compiles without critical warnings – Testbench passes all functional cases provided – Bitstream operate...

I need a CPM GMSK demodulator implemented in VHDL for a signal processing system. Targeting data rates of 8 Mbps with system clock of ~100 MHz Key Requirements: - VHDL expertise - Experience with CPM and GMSK modulation/demodulation - Background in signal processing Ideal Skills: - Ability to meet high bit rate requirements - Knowledge of hardware integration Please provide relevant experience and approach.

I'm seeking an experienced FPGA developer who can assist with design and development, specifically in HDL coding, using both VHDL and Verilog. Ideal Skills and Experience: - Proficiency in both VHDL and Verilog - Strong background in FPGA architecture - Experience in integrating and interfacing FPGAs with other systems - Ability to test, debug, and optimize designs Please provide relevant project experience and a brief portfolio. Looking forward to your bids!

I need an experienced FPGA programmer to assist with a data processing application. Key Requirements: - Proficiency in at least one of the following FPGAs: Xilinx, Altera, Lattice - Expertise in data processing applications - Familiarity with VHDL, Verilog, or SystemVerilog Ideal Skills and Experience: - Proven track record in FPGA programming - Strong background in data processing algorithms - Ability to work with various FPGAs and HDLs Please provide relevant experience in your bids. We need to develop ethernet hub in fiber optic 2 ports , and 16 SPI for chip led controller using data and clock . SPecia Ethernet protocol defined by us.

...are building a hardware-accelerated probabilistic engine that runs QUBO/Ising workloads for Logistics, Finance, and Cyber-Intelligence, and I’m open to engaging specialists across several tracks: • ML Engineer – craft graph neural networks and matrix-compression pipelines that translate complex optimisation problems into sparse, hardware-friendly representations. • FPGA Engineer – write VHDL/Verilog kernels for AWS F1, pushing the solver to micro-second latency. • Backend Architect – design a high-performance API layer in Go, Rust or Python that orchestrates FPGA instances, manages job queues and exposes REST/gRPC endpoints. • Cyber-Security Expert – conduct cryptanalysis and network-intelligence research to harden...

I am building a Verilog-based, real-time Sobel edge detector that streams video from an OV7670 camera to a monitor over VGA on a Nexys A7-100T board, all within Xilinx Vivado. The architectural concept is clear, yet the project’s success now depends on rigorous simulation, validation, and concise documentation suitable for an academic submission. Your main focus will be designing an efficient test and simulation strategy: self-checking test-benches, frame-level functional coverage, timing verification, and any other diagnostics that prove the design meets real-time performance. I am open to whichever simulation environment you consider best—whether you stay inside Vivado’s integrated simulator or introduce ModelSim, Verilator, or another workflow—provided it...

...implement multiplexers and demultiplexers. The goal is to move from logic-level concepts all the way to a working circuit that can be demonstrated in the lab. Here is what I’d like from you: • A clear derivation of the truth tables, Boolean expressions, and any Karnaugh-map (or equivalent) minimisation that leads to the final gate-level schematic. • An HDL version of the same circuit (Verilog or VHDL—whichever you prefer) that compiles cleanly and is ready for simulation. • Simulation results that verify correct operation for every input combination; ModelSim, Vivado, Quartus, or Logisim waveforms are all acceptable. • Brief, well-commented documentation so I can present the design during our tutorial session and explain each decisio...

I need a synthesizable, timing-clean Verilog implementation of the classic MUSIC (Multiple Signal Classification) algorithm that can estimate the direction of arrival of one or more narrow-band signals received on a uniform linear array of four antennas. The end use is a radar front-end, so accuracy takes priority over latency or power. Scope • Design the fixed-point signal-processing chain on an FPGA (I am currently working with Xilinx Series parts; feel free to suggest an equivalent if it helps meet timing). • Implement covariance matrix formation, eigen decomposition and the pseudospectrum peak search entirely in hardware; no soft-core processors or external DSP chips. • Include provisions for array calibration coefficients so the design can be tuned on-si...

I need clean, well-documented VHDL that implements a set of simple digital circuits on an FPGA. The task sits firmly in the Digital circuits design space—no signal-processing tricks or embedded firmware layers—just straightforward gate-level logic and a few flip-flops brought to life in hardware. Here is what I expect: • VHDL source files for each module • A small, self-checking testbench that runs in ModelSim/Questa or an equivalent simulator • Clear synthesis-ready code that fits easily onto a mid-range Xilinx or Intel development board (the exact board can be generic; resources should stay minimal) • A short README outlining how to simulate, synthesize, and pin-map the design Because the scope is intentionally simple, I value concis...

...verification. • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. • Work on functional & code coverage verification. • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 6years of ASIC design verification experience • Experience / Background with DDR or Memory Controller. PHY Verification is a plus • Experience with scripting languages like Python, Perl and TCL is a plus. • Collaborate with architects, hardware...

...verification. • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. • Work on functional & code coverage verification. • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 6years of ASIC design verification experience • Experience / Background with DDR or Memory Controller. PHY Verification is a plus • Experience with scripting languages like Python, Perl and TCL is a plus. • Collaborate with architects, hardware...

I need a fully-synthesizable VHDL implementation of a single-system GPS L1 C/A receiver that carries the signal all the way from raw I/Q samples through acquisition, tracking, navigation decoding, and a basic PVT solver that delivers standard-accuracy position, velocity, and time. The acquisition stage must use a true parallel-search architecture; serial search or matched-filter alternatives are out of scope for this project. The code has to be cleanly structured, well-commented, and accompanied by self-checking test benches that exercise every major block—acquisition engine, tracking loops (DLL, PLL/FLL), data demodulator, ephemeris parser, and the fixed-point PVT routine. Simulation should run in Vivado or an equally common VHDL simulator, with clear instructions on ...

I'm seeking an experienced FPGA developer to help debug logical errors in existing VHDL code for a Lattice Semiconductor MachX03 development board. Key Requirements: - Expertise in VHDL - Experience with Lattice Semiconductor FPGAs - Strong debugging skills, especially with logical errors Ideal Skills and Experience: - Proven track record in FPGA development and debugging - Familiarity with MachX03 specific features and tools - Ability to provide clear, concise solutions and documentation Looking forward to your expertise!

...production contract covering up to 8,000 diagrams, with further scale potential. Project Overview The objective is to collect and deliver technical diagram images representing electrical and digital design concepts, paired with either: Verilog HDL code, or Clear, structured technical explanations in English These assets will be used in advanced AI/ML and engineering research applications. Dataset Requirements Each diagram must conform to one of the following variants: Variant 1 Original technical diagram image Corresponding Verilog Hardware Description Language (HDL) code Variant 2 Original technical diagram image Detailed English technical description explaining the circuit’s function and behavior All diagrams must be original and bui...

I have already begun converting the VHDL Language Reference Manual—about 700 pages—from its original PDF to LaTeX, but only scattered portions are finished. Roughly the first nine sections of the thirty-four total have a draft translation; the rest is still untouched or only partially copied over. All existing .tex sources, my compile script, and the official style guidelines (custom class file, macro set, and layout notes) will be in the hand-off package so you can follow the exact formatting rules that match the published standard. Figures, tables, and cross-references must render cleanly under pdflatex without manual post-processing. What I need from you is the full, consistent LaTeX source that: • covers every remaining section and appendix, completing the 70...

...tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative. Roles we still need to fill (4+ yrs exp each) System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring;...

...tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative. Roles we still need to fill (4+ yrs exp each) System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring;...

...multi-disciplinary expert or a small team to assist in a high-fidelity hardware research project focused on PCIe device emulation and DMA-based memory forensics. The goal is to develop a custom FPGA-based solution that can perfectly mimic a legitimate consumer PCIe device (e.g., Network or Storage Controller) to pass low-level system integrity checks. Key Responsibilities: Emulation (FPGA/Verilog): Develop custom firmware for an Artix-7/35T/75T FPGA board to emulate a real-world donor device's configuration space and TLP behavior. Development (C/C++): Create a high-performance Windows/Linux driver for direct memory access via the PCIe bus, ensuring stability and low latency. Analysis: Design a system to read and analyze specific application memory segments in real-time

I need a digital-only control circuit taken from concept through a production-ready schematic. The task sits firmly in the circuit-design branch of electrical engineering: no analog front-end...straight to PCB layout later. • Provide accompanying design files: schematics, netlist, component libraries, and a concise design-rules document. • Run basic simulations or logic-timing checks to verify that the circuit meets the specified control timings before hand-off. Everything should stay purely digital; no mixed-signal blocks are expected at this stage. If you are comfortable with Verilog/VHDL for behavioural validation, that is a plus but not mandatory—the key deliverable is a schematic ready for layout and prototyping. Let me know your favourite toolchain ...

I need a digital-only control circuit taken from concept through a production-ready schematic. The task sits firmly in the circuit-design branch of electrical engineering: no analog front-end...straight to PCB layout later. • Provide accompanying design files: schematics, netlist, component libraries, and a concise design-rules document. • Run basic simulations or logic-timing checks to verify that the circuit meets the specified control timings before hand-off. Everything should stay purely digital; no mixed-signal blocks are expected at this stage. If you are comfortable with Verilog/VHDL for behavioural validation, that is a plus but not mandatory—the key deliverable is a schematic ready for layout and prototyping. Let me know your favourite toolchain ...

I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.

I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.