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    1,361 verilog project online work trabajados encontrados, precios en USD

    necesito transmitir datos numericos entre la fpga ne...ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un plazo de 15 dias.

    $32 / hr (Avg Bid)
    $32 / hr Oferta Promedio
    6 ofertas

    Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.

    $23409 - $58522
    $23409 - $58522
    0 ofertas

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $19 / hr (Avg Bid)
    $19 / hr Oferta Promedio
    4 ofertas

    ...i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am currently

    $154 (Avg Bid)
    $154 Oferta Promedio
    4 ofertas

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    $4470 (Avg Bid)
    $4470 Oferta Promedio
    24 ofertas

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $390 (Avg Bid)
    $390 Oferta Promedio
    3 ofertas

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    $65 (Avg Bid)
    $65 Oferta Promedio
    18 ofertas

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Oferta Promedio
    16 ofertas

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
    $23 Oferta Promedio
    18 ofertas

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [iniciar sesión para ver URL]

    $46 (Avg Bid)
    $46 Oferta Promedio
    16 ofertas

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
    $23 Oferta Promedio
    22 ofertas

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
    $22 Oferta Promedio
    17 ofertas
    Verilog design project Finalizado left

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
    $21 / hr Oferta Promedio
    20 ofertas

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
    $131 Oferta Promedio
    19 ofertas

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
    $122 Oferta Promedio
    13 ofertas
    System Verilog Trainer Finalizado left

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1988 (Avg Bid)
    $1988 Oferta Promedio
    5 ofertas

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
    $100 Oferta Promedio
    8 ofertas

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $122 (Avg Bid)
    $122 Oferta Promedio
    19 ofertas
    Alarm clock Verilog Finalizado left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
    $184 Oferta Promedio
    15 ofertas

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
    $86 Oferta Promedio
    5 ofertas