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    1,385 verilog project online work trabajados encontrados, precios en USD

    necesito transmitir datos numericos entre la fpga ne...ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un plazo de 15 dias.

    $32 / hr (Avg Bid)
    $32 / hr Oferta Promedio
    6 ofertas

    Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.

    $23409 - $58522
    $23409 - $58522
    0 ofertas

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    $78 (Avg Bid)
    $78 Oferta Promedio
    5 ofertas
    Task on verilog 3 bit ALU 5 días left
    VERIFICADO

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    $48 (Avg Bid)
    $48 Oferta Promedio
    16 ofertas

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    $28 (Avg Bid)
    $28 Oferta Promedio
    3 ofertas

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $122 (Avg Bid)
    $122 Oferta Promedio
    21 ofertas

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
    $16 / hr Oferta Promedio
    29 ofertas

    I have project ready already just need some help!

    $194 (Avg Bid)
    $194 Oferta Promedio
    9 ofertas

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    $19 (Avg Bid)
    $19 Oferta Promedio
    6 ofertas

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    $33 (Avg Bid)
    $33 Oferta Promedio
    3 ofertas

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    $140 (Avg Bid)
    $140 Oferta Promedio
    7 ofertas

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    $121 (Avg Bid)
    $121 Oferta Promedio
    17 ofertas

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    $500 (Avg Bid)
    $500 Oferta Promedio
    15 ofertas

    Please refer the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    $43 (Avg Bid)
    $43 Oferta Promedio
    13 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $176 (Avg Bid)
    $176 Oferta Promedio
    12 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $149 (Avg Bid)
    $149 Oferta Promedio
    4 ofertas

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $414 (Avg Bid)
    $414 Oferta Promedio
    2 ofertas
    DSP48E1 help Finalizado left

    Hi! I need some help with DSP48E1 verilog instantiation.

    $4 / hr (Avg Bid)
    $4 / hr Oferta Promedio
    5 ofertas
    I want clients Finalizado left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    $18 (Avg Bid)
    $18 Oferta Promedio
    2 ofertas

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    $152 (Avg Bid)
    $152 Oferta Promedio
    7 ofertas

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    $38 (Avg Bid)
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    111 ofertas
    verilog project Finalizado left

    verilog coding using putty or terminal. if you are interested i will give more information.

    $135 (Avg Bid)
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    27 ofertas
    System verilog Finalizado left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    $97 (Avg Bid)
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    8 ofertas
    verilog project Finalizado left

    mtech Verilog project

    $21 (Avg Bid)
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    19 ofertas

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    $180 (Avg Bid)
    $180 Oferta Promedio
    7 ofertas

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    $2830 (Avg Bid)
    $2830 Oferta Promedio
    15 ofertas

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    $104 (Avg Bid)
    $104 Oferta Promedio
    12 ofertas

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    $101 (Avg Bid)
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    2 ofertas

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $20 / hr (Avg Bid)
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    9 ofertas
    verilog assignment Finalizado left

    ...i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am currently

    $131 (Avg Bid)
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    12 ofertas

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    $4436 (Avg Bid)
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    27 ofertas

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $390 (Avg Bid)
    $390 Oferta Promedio
    3 ofertas

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    $65 (Avg Bid)
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    18 ofertas

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Oferta Promedio
    16 ofertas

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
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    18 ofertas

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [iniciar sesión para ver URL]

    $46 (Avg Bid)
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    16 ofertas

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
    $23 Oferta Promedio
    21 ofertas

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
    $22 Oferta Promedio
    17 ofertas
    Verilog design project Finalizado left

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
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    20 ofertas

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
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    19 ofertas

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
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    13 ofertas
    System Verilog Trainer Finalizado left

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1988 (Avg Bid)
    $1988 Oferta Promedio
    5 ofertas

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
    $100 Oferta Promedio
    8 ofertas

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $122 (Avg Bid)
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    19 ofertas
    Alarm clock Verilog Finalizado left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
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    15 ofertas

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
    $86 Oferta Promedio
    5 ofertas

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
    $106 Oferta Promedio
    11 ofertas

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
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    7 ofertas

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [iniciar sesión para ver URL] Using PG236 [iniciar sesión para ver URL]

    $128 (Avg Bid)
    $128 Oferta Promedio
    3 ofertas

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $72 (Avg Bid)
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    1 ofertas