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    1,442 verilog project online work trabajados encontrados, precios en USD

    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

    $227 (Avg Bid)
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    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

    $242 (Avg Bid)
    $242 Oferta Promedio
    4 ofertas

    necesito transmitir datos numericos entre la fpga ne...ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un plazo de 15 dias.

    $32 / hr (Avg Bid)
    $32 / hr Oferta Promedio
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    Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.

    $23409 - $58522
    $23409 - $58522
    0 ofertas

    Hello freelancers! The goal of this project is to help us investigate hardware-efficient implementation of the Espresso stream cipher and to compare it to Grain-128 and Trivium in terms of area, delay, latency and power energy consumption so we can decide which suits us the best. Your tasks will include: • Investigating hardware optimization

    $197 (Avg Bid)
    $197 Oferta Promedio
    2 ofertas

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    $56 (Avg Bid)
    $56 Oferta Promedio
    24 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1035 (Avg Bid)
    $1035 Oferta Promedio
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    ...to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [iniciar sesión para ver URL]; a. The source can be taken as

    $625 (Avg Bid)
    $625 Oferta Promedio
    3 ofertas
    find fpga projects Finalizado left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    $462 (Avg Bid)
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    10 ofertas
    Matlab Codnig Finalizado left

    I need the matlab developer and verilog developer

    $625 (Avg Bid)
    $625 Oferta Promedio
    17 ofertas
    16-point FFT Finalizado left

    verilog code for radix-4 16 point fft

    $15 (Avg Bid)
    $15 Oferta Promedio
    8 ofertas

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    $16 (Avg Bid)
    $16 Oferta Promedio
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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $11854 (Avg Bid)
    $11854 Oferta Promedio
    2 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $10386 (Avg Bid)
    $10386 Oferta Promedio
    1 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $894 - $901
    $894 - $901
    0 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $882 - $882
    $882 - $882
    0 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $884 - $884
    $884 - $884
    0 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $896 (Avg Bid)
    $896 Oferta Promedio
    3 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $736 - $883
    $736 - $883
    0 ofertas
    reviewing a code Finalizado left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

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    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    $150 (Avg Bid)
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    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    $156 (Avg Bid)
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    6 ofertas
    Verilog Expert Finalizado left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    $61 (Avg Bid)
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    20 ofertas

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

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    6 ofertas

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    $140 (Avg Bid)
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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    $26 Oferta Promedio
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    $29 Oferta Promedio
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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $179 (Avg Bid)
    $179 Oferta Promedio
    7 ofertas

    Need help program FPGA with Artix-7 using Verliog.

    $125 (Avg Bid)
    $125 Oferta Promedio
    5 ofertas

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    $175 (Avg Bid)
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    1 ofertas

    Implement the Zen Protocol in the FPGA and update the Mining App

    $1220 (Avg Bid)
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    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    $25 (Avg Bid)
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    Make a serial interface system using Verilog

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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    $197 (Avg Bid)
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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    $147 (Avg Bid)
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    5 ofertas

    Design of a signal generator using verilog hdl. Should be done using Vivado Design Suite . More details in chat.

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    image water marking Finalizado left

    image watermarking baed on dct algorithm in verilog code, need to implement in xilinx board

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    Part 1: Dynamic Patterns Using LEDs Requirement In this part, you are required to write a Verilog code that produces at least four different dynamic patterns, that is changing with time with reasonable speed. And those patterns are controlled by switches. Features • Use the most left switches to change the patterns. • Design your own patterns. • Use

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    Verilog game Finalizado left

    I have a verilog game. I need a freelancer to change the resolution of the game and add a background.

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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    I want to implement the Ethernet connection. The deliverables are as follows -Verilog code to run on a Spartan 6 Board - (xc6slx100) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

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    Simple project, that basically should detail the observed waveforms and max frequency of given code.

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    Project for Behailu D. Finalizado left

    Hi Behailu D., I noticed your profile and would like to offer you my project. We can discuss any details over chat. conversion python to verilog

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    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    $174 (Avg Bid)
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    8-bit Calculator Finalizado left

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

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    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

    $155 (Avg Bid)
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    Matlab to Verilog Finalizado left

    Code needs to be ported from Matlab to Verilog

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    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

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